x86: Enable TSC_RELIABLE for AMD servers
authorKeir Fraser <keir.fraser@citrix.com>
Fri, 23 Oct 2009 09:15:17 +0000 (10:15 +0100)
committerKeir Fraser <keir.fraser@citrix.com>
Fri, 23 Oct 2009 09:15:17 +0000 (10:15 +0100)
commitdef87a2cbf0f4aacd6cd68d2c56ea58cc03a6b62
treeaec69231be6bdb402dfa9fe481fe30342dd27297
parentd6d3c05250536f81aa988207fc83c4a3a7cccb6a
x86: Enable TSC_RELIABLE for AMD servers

Except for a published BIOS errata on family 11h processors,
all AMD servers that have the Invariant TSC bit set have
a reliable TSC so Xen should not write to the TSC.

Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com>
Acked-by: Mark Langsdorf <mark.langsdorf@amd.com>
xen/arch/x86/cpu/amd.c